The present invention is directed to the fabrication of transistors, such as Complementary Metal Oxide Silicon (CMOS) transistors, having lightly doped drain (LDD) regions and, more particularly, to such transistors which include an oxide spacer etch after a disposable nitride spacer removal so that ultra shallow LDD junctions may be achieved.
A field-effect transistor is a semiconductor device which depends on the control of current by an electric field for its operation. There are two types of field-effect transistors: the junction field-effect transistor (JFET or FET) and the metal-oxide-semiconductor field-effect transistor (MOSFET).
Field-effect transistors may be N-channel or P-channel type. Current is caused to flow along the length of a semiconductor bar of the N-type or P-type material when a voltage supply is connected between the two ends of a channel of the bar. The current is comprised of majority carriers, which are typically electrons. The source is the terminal through which the majority carriers enter the bar, while the drain is the terminal through which the majority carriers exit the bar. On both sides of the bar, heavily doped regions of acceptor impurities are formed by, for example, alloying or diffusion. These regions are called gates. Between a gate and the source, a voltage is applied to reverse-bias the P-N junction. The region of the bar between the two gate regions is the channel. The majority carriers move through the channel from the source to the drain.
In a JFET, an electric field is applied to the channel through a P-N diode. In a MOSFET, a metal gate electrode is utilized, which is separated from the semiconductor channel by an oxide layer. In this manner, the metal-oxide-semiconductor allows an electric field to effect the channel if an external potential is applied between the gate and the substrate.
There are two types of MOSFET transistors: a depletion MOSFET and an enhancement MOSFET. For the depletion MOSFET, at zero gate voltage and a fixed drain voltage, the current is at a maximum and then decreased with applied gate potential. For the enhancement MOSFET, there is no current at zero gate voltage and the output current increases with an increase in gate potential.
Additionally, a complementary MOS (CMOS) device is a device which has both P-channel and N-channel enhancement on the same chip.
In the construction of MOSFET devices, lightly doped drain (LDD) regions have commonly been used to reduce the hot electron effect in a FET. This is made possible by providing LDD regions in the substrate which separate the more heavily doped source and drain regions from the channel region of the substrate, thereby reducing the electric field at the source and drain pinch-off regions, and thus increasing the channel breakdown voltage and reducing electron impact ionization (hot electron effects). LDD regions are typically formed on both sides of the channel, since either of the source/drain regions are capable of functioning as a drain region, depending upon how the device is later electrically connected to the reminder of the integrated circuit structure.
A FET having LDD regions is typically fabricated in an active region of a substrate. The active region has a P-type background doping and is bounded by field oxide (FOX) regions which electrically isolate the FET from other devices formed in the same substrate. To form a FET with a LDD region, a disposable spacer approach may be used. A spacer material layer is formed over the entire structure and etched so that spacers remain at the ends of the gate. These spacers overlie portions of the active regions adjacent to the gate structures. Thereafter, a first implant is performed with a heavy dose of a P-type or N-type dopant to form P+ source and drain regions or N+ source and drain regions, respectively. During this implant, the spacers mask the underlying active regions. The underlying active regions which do not receive the second implant become the LDD regions. Thus, the width of the spacers define the width of the LDD regions. Then, after the disposable spacers have been removed, a second implant is performed with a lighter dose of a P-type or N-type dopant to form Pxe2x88x92 LDD regions or Nxe2x88x92 LDD regions, respectively.
One manner of forming spacers is to perform a dry etch of a spacer layer, typically a silicon nitride (Si3N4) layer. In particular, after the deposition of an etch stop layer, typically an oxide layer, the spacer layer is deposited over the substrate, the gate, and the field oxide regions, and is subsequently etched isotropically to provide the spacers. An etchant is selected which isotropically etches the spacer layer and will stop etching on the etch stop layer. The etchant that removes the spacers will also stop on the etch stop layer due to the etch selectivity difference.
Typical masking steps include a N+ mask to form N+ source and drain regions, P+ mask to form P+ source and drain regions, a Nxe2x88x92 mask to form lightly doped Nxe2x88x92 regions and a Pxe2x88x92 mask to form lightly doped Pxe2x88x92 regions. A mask is a transparent support material coated with a thin layer of opaque material. Certain portions of the mask are moved, leaving opaque material on the mask in the precise pattern required on the silicon surface. More particularly, the openings of the mask correspond to the areas where it is desired to remove the silicon dioxide from the silicon surface. Each masking step typically includes the sequential steps of preparing the substrate, applying the photoresist material, soft-baking, aligning and isotropically exposing the photoresis to radiation by using a mask, baking, hard baking, developing the patterns in the resist, hard baking, implanting a desired dose of a dopant with the required conductivity type, stripping the photoresist, and then cleaning the substrate.
Previously, LDD implant could be achieved to a depth on the order of 300 Angstroms to 700 Angstroms. Moreover, the depth of the LDD junction varied due to the non-uniformity of the layer of liner oxide. Accordingly, there is a need for an ultra shallow LDD implant which improves the uniformity of the junction depth as the non-uniformity of the liner oxide layer is eliminated.
One aspect of the invention provides a method of fabricating a transistor having a lightly doped drain region. The first step is to form a gate having side edges in an active region of a substrate, where the gate overlies a portion of the active region. The next step is to form an oxide layer over the gate. Then, a nitride layer is formed over the oxide layer. The next step is to isotropically etch the nitride layer to form sidewall spacers about the side edges of the gate. Then, heavily doped source and drain regions are implanted into the substrate and about the side edges of the gate using the nitride sidewall spacers. The nitride sidewall spacers are then removed. The oxide layer is then isotropically etched to form thin oxide spacers. Then, lightly doped drain regions are implanted between the side edges of the gates and the heavily doped drain regions. The oxide layer is preferably etched using an isotropic dry etch so that the edge of the gate oxide will not be attacked. The chemistry of the gas used in this dry etch is, preferably, CF4:CHF3:Ar. Because of the oxide spacer etch step, the lightly doped drain region is implanted to an ultra shallow level of depth, to the range of about 150 Angstroms to about 300 angstroms. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the oxide etch stop layer is eliminated.
Another aspect of the present invention provides a method of fabricating a complementary MOS transistor having a lightly doped drain region. The first steps are to form a first gate, which has side edges, in a first active region of a substrate and to form a second gate, which also has side edges, in a second active region of the substrate. An oxide layer is then formed over the substrate including the first and second gates. A spacer material layer is then formed over the oxide layer and the substrate, including the first and second gates. Preferably, the spacer material layer is composed of nitride. The nitride layer is then isotropically etched with respect to the oxide layer to form nitride sidewall spacers about the side edges of the first and second gates. Heavily doped source and drain regions of the first and the second conductivity type are then implanted sequentially into the substrate using two different masks and using the nitride sidewall spacer masks. The nitride sidewall spacers are then removed along the side edges of the gates. The oxide layer is then isotropically etched to form thin oxide spacers along the side edges of the gates. Lightly doped drain regions of the first and the second conductivity type are then implanted sequentially along the side edges of the gates between the gates the heavily doped drain regions using two different masks. The oxide layer is preferably etched using an isotropic dry etch so that the edge of the gate oxide will not be attacked. The chemistry of the gas used in this dry etch is, preferably, CF4:CHF3:Ar. The oxide spacer is preferably thin in width, in the range of about 60 Angstroms to about 100 Angstroms. Because of the oxide spacer etch step, lightly doped drain regions are implanted to an ultra shallow level of depth, to the range of about 150 Angstroms to about 300 Angstroms. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the oxide etch stop layer is eliminated.
These and other objects, advantages, and features of the present invention will be better understood upon review of the following detailed description of the preferred embodiments.